Biography
Hi 👋, I’m Hammad
I’m an incoming Hardware Security researcher at PSec Lab, Penn State University under the supervision of Prof. Arslan Khan.
I’ve contributed to RISC-V compliance verification and embedded systems, working on tools like RISCOF, the RISC-V Sail model, and RISC-V Architectural Tests.
Currently, I’m exploring firmware analysis, reverse engineering, and microarchitectural attacks.
📫 Feel free to reach out for research collaborations!
Interests
- Hardware Security
- Firmware Analysis
- Computer Architecture
- Design Verification Techniques
Education
PhD Computer Science, 2025 - Present
The Pennsylvania State University
BSc Electrical Engineering, 2020 - 2024
University of Engineering and Technology (UET), Lahore
Publications
*
Verification of CoreSwap: Replacing ARM Cortex-A5 with RISC-V CVA6 in ARM SoC Environment.
RISC-V Summit Europe, Paris, France,
2025.
Comprehensive Verification of the RISC-V Memory Management Unit: Challenges and Solutions.
RISC-V Summit Europe, Paris, France,
2025.
Enhancing Privilege Architecture Support in RISC-V ISAC.
RISC-V Summit Europe, Munich, Germany,
2024.
Experience
Design Verification Engineer
- Collaborated with Mr. Allen Baum, Vice-Chair of the RISC-V ISA Infrastructure Horizontal Committee, on a open-source project to enhance Privilege Architecture support in the RISC-V ISAC, a key coverage tool within the RISCOF compliance framework.
- Developed a translator within the RISC-V ISAC to optimize the input CGF format (derived from YAML), significantly reducing covergroup size for users and improving tool efficiency.
- Authored covergroups for Physical Memory Protection and assisted Mr. Umer Shahid, Vice-Chair of the RVI Architecture Test SIG WG, in writing RISC-V assembly tests for Physical Memory Protection, contributing to the robustness of the compliance suite.
- Contributed to the completion of the SV32 Virtual Memory test plan for CVA6, ensuring its alignment with RISC-V specifications.
Associate Design Verification Engineer
- Successfully completed a rigorous 6-month training program in SystemVerilog for Verification, acquiring a robust foundation in advanced verification techniques.
- Completed coursework in advanced Computer Architecture and RISC-V assembly, expanding knowledge and technical expertise.
- Contributed to the verification efforts of the AMBA - AHB3 Lite Protocol, gaining practical experience in protocol verification.
Lab Assistant
Digital Systems Design Lab, UET Lahore
- Facilitated lab sessions and mentored students, contributing to the development of course materials. Created instructional content and delivered personalized support to enhance students’ understanding of SystemVerilog and application of course concepts.
Summer Research Intern
Digital Systems Design Lab, UET Lahore
- Engaged in hands-on experience with System Verilog, focusing on the RISC-V-based open-source CVA6 core.
- Worked on manual synthesis of RTL-level diagrams from SystemVeriog code, contributing to in-depth analysis and understanding of digital systems and design.