Experience

RTL NOT a Design Engineer

Jun 2021 – Aug 2023

Design and implement micro-architectural improvements for a 6stage in-order RISC-V Cores.
Design Multi-core RISC-V processor with hierarchial and coherent Caches.
Conceptualised and directed implementation of various features for key tools in the RISC‐V Architectural Testing ecosystem for testing various extensions in the specification.

RTL Design Intern

Dec 2020 – May 2021

Research Intern

SHAKTI initiative, RISE Labs

May 2020 – Oct 2020 IIT Madras

Designed and implemented a secure boot solution for Shakti RISC‐V cores. The solution consisted of a signing tool, framework and run‐time libraries to be integrated with the firmware.
Designed extensions to support higher level API calls and provide better security guarantees.
Proposed a scheme to support trusted execution environments using a co‐processor by analysing various solutions such as Intel SGX, Sanctum and Keystone.

Summer Research Intern

SHAKTI initiative, RISE Labs

May 2019 – Jul 2019 IIT Madras

Evaluated various methods to generate bluespec code for SOCs based on a given configuration. Implemented a tool which could automatically generate SOCs with optimal address mappings for heterogeneous and hierarchical busses.
Identified key csr configuration options in the RISC‐V ISA and designed a scheme to describe the custom behaviours. Implemented an open‐source tool(riscv-config) in python to validate descriptions and verify legality of behaviours.
Evaluated various strategies for RISC‐V architectural compliance testing and implemented a dynamic, scalable and easy‐to‐use open‐source framework(riscof) based on the best strategy.

Research Intern

SHAKTI initiative, RISE Labs

May 2018 – Jul 2018 IIT Madras

Designed and developed a pipelined and multi‐cycle SHA 256 accelerator in Bluespec System Verilog.
Optimised the design for area, delay and power on the Xilinx Artix‐7 FPGA.
Verified the correctness using NIST test vectors