RISCOF, a Python-based framework, ensures RISC-V processor implementations comply with instruction set simulators like Spike and Sail. It supports both manual and automated test suite generation via RISC-V CTG, with coverage analysis performed through RISC-V ISAC. However, the coverage analysis of privilege architectural tests has been limited due to incomplete support in RISC-V ISAC. To address this, we have introduced new features in RISC-V ISAC specifically for privileged architecture, along with a more efficient method for writing coverpoints. These enhancements aim to improve compliance testing comprehensively.