Poster

Verification of CoreSwap: Replacing ARM Cortex-A5 with RISC-V CVA6 in ARM SoC Environment
This paper presents the verification methodology and results of the CoreSwap project, where the ARM Cortex-A5 core in ARM Educational …
Muhammad Hammad Bashir, Umer Shahid, Muhammad Tahir, Yazan Hussnain, Fatima Saleem
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Comprehensive Verification of the RISC-V Memory Management Unit: Challenges and Solutions
The Memory Management Unit (MMU), critical for virtual memory translation and protection, demands rigorous verification due to its …
Huda Sajjad, Muhammad Hammad Bashir, Yazan Hussnain, Fatima Saleem
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Enhancing Privilege Architecture Support in RISC-V ISAC
RISCOF, a Python-based framework, ensures RISC-V processor implementations comply with instruction set simulators like Spike and Sail. …
Muhammad Hammad Bashir, Umer Shahid, Allen Baum, S Pawan Kumar
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