CV

Design Verification Engineer

10xEngineers

• Collaborated with Allen Baum on open-source work enhancing privileged architecture support in RISC-V ISAC, a coverage tool within the RISCOF compliance framework.
• Developed a translator to optimize the input CGF format derived from YAML, reducing covergroup size and improving tool efficiency.
• Authored Physical Memory Protection covergroups and assisted with RISC-V assembly tests for PMP.
• Contributed to the SV32 virtual memory test plan for CVA6.

Associate Design Verification Engineer

10xEngineers

• Completed training in SystemVerilog for verification, advanced computer architecture, and RISC-V assembly.
• Contributed to AMBA AHB3-Lite protocol verification.

Lab Assistant

Digital Systems Design Lab, UET Lahore

• Mentored students and contributed instructional content for SystemVerilog and digital systems coursework.

Summer Research Intern

Digital Systems Design Lab, UET Lahore

• Worked with the RISC-V-based open-source CVA6 core.
• Manually synthesized RTL-level diagrams from SystemVerilog to support digital systems analysis.

PhD

The Pennsylvania State University

Computer Science

• Researcher in PSec Lab advised by Prof. Arslan Khan.

BSc

University of Engineering and Technology (UET), Lahore

Electrical Engineering

Verification of CoreSwap: Replacing ARM Cortex-A5 with RISC-V CVA6 in ARM SoC Environment

RISC-V Summit Europe 2025 - Posters

Comprehensive Verification of the RISC-V Memory Management Unit: Challenges and Solutions

RISC-V Summit Europe 2025 - Posters

Enhancing Privilege Architecture Support in RISC-V ISAC

RISC-V Summit Europe 2024 - Posters